8 ,. analog -.. devices - - preliminary technical data features resolution: :1:4 1/2 digits bcd or f20k count binary capa- bility for 5 1/2 digit resolution or custom data formats data format: multiplexed bcd (for display) and serial count (for external linearization, data reformatting, or micro- processor interface) accuracy: :1:1 count in :l:20k counts scale factor drift: 0.2ppmfc- using only medium- precision op amps requires only a single positive reference overrange display auto calibration capability interfaces to ttl or 5v cmos hold input and scc (system conversion complete) output for interface flexibility 8 general description the ad7555 is a 4 1/2 digit, monolithic cmos, quad slope integrating adc subsystem designed for display or micro- processor interface applications. use of the high resolution enable input expands the display form~t to 5 1/2 digits bcd. with sco (serial count out) connected to sci (serial count in), the output data format is multiplexed bcd suitable for visual display purposes. as an added feature, sco can also be used with rate multipliers for linearization, or with bcd or binary counters for data reformatting (up to 200k binary counts). the quad slope conversion algorithm (analog devices patent no. 3872466) converts the external amplifier's input drift errors to a digital number and subsequently reduces the total system drift error to a second order effect. using only inex- pensive, medium-precision amplifiers a scale factor drift of o.2ppmf c is achieved. ~ pin configuration vref> f1l . 8 151 $c1 ad7555 top view information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implica- tion or otherwise under any patent or patent rights of analog devices. cmos 4y2 /5y2 digit adc subsystem ." ad7555 functional diagram vref> ( 1 , os . do , data strobe ,b8 b4, b2 bj , bcd data ordering informa non -- model ad7555bd t 0 . i peratmg package i temperature range ~~- " 28 pin side brazed ceramic -25c to +85c -.j --- 0 to +70oc -- ,- -- ad7555kn 28 pin molded plastic - - ~ route 1 industrial park; p.o. box 280; norwood, mass. 02062 tel: 617/329-4700 1wx: 710/394-6577 west coast mid-west texas 714/842-1717 312/894-3300 214/231-5094 obsolete
-2- specifications (vcc = +5v, vss = -5v, vrefl = +4.0960v, fclk = 614.4khz, agnd = ov) limit at limit at ta parameter ta = +2soc = tmin' tmax units conditions/comments 8 analog switches ron (switch 1-3) 800 1200 f2 max -2valn+2v refer to functional diagram l'lron (switch i) versus aln 300 500 f2 typ -2valn+2v mismatch between any two switches (excluding swo) 300 500 f2 typ -2valn+2v llkg (switch off) swo (pin 6) 1 70 na max irjct (pin 5) = +2.048v ovlrout (pin s)+10v swi (pin 2) 1 70 na typ ain = +2v to -2v, bufln = ov and +4.096v sw2 (pin 3) 1 70 na typ agnd = ov, bufin = -2v to +2v, +4.096v sw3 (pin 1) 1 70 na typ vrefl = +4.096v, bufin = -2v to +2v (bufin, 4) 3 200 na 1 of sw1, 2, 3 on control inputs (pins 7, 8, 9,15) vinh 3.0 3.0 vmin vinl 0.8 0.8 vmax iinh or iinl 1 10 j1a max vin = ov or vcc clock inputs (pin 12 and 13) vinh (clk) 3.5 3.5 vmin vinl (clk) 0.8 0.8 vmax vinh (dmc) 3.0 3.0 vmin vinl (dmc) 0.8 0.8 vmax iinh (clk) 1.0 1.5 ma max iinl (clk) -1.0 -1.5 mamax iinh (dmc) 200 300 j1a max iinl (dmc) -100 -150 j1a max digital outputs do - os (pins 22-27) 8 voh 4.5 4.5 vmin isource = 40j1a vol 4.0 4.0 vmax isink = sma (display driver load) vol 0.5 0.8 vmax isink= 1.6ma (ttl load) b1, b2, b4, b8, dav, scc, sco (pins 20,19,18,17,10,11,16) voh 4.0 4.0 vmin isource = 40j1a vol 0.5 0.8 vmax isink = 1.6ma dynamic performance dmc pulse width 5 5 j1s mm see figure 3 dmc frequency 100 100 khz max typical fomc is 1.skhz with comc = o.olj1f clk frequency 1.5 1.5 mhz max propagation delay dmc high to da v high 5 7 j1s max see figure 3 dmc high to da v low 5 7 j1s max dmc high to bcd data on b8,b4, b2, bl 5 5 j1s max dmc low to digit strobe (do -os) low 5 5 .. /ls max power supply icc 5 5 ma max dunng conversion lss 5 5 ma max during conversion v cc range +sw+17 +sto+17 v see absolute maximum ratings vss range -5 to -17 -sto-17 v specifications subject to change without notice. 8 obsolete
8 8 -- i , i l- absolute maximum ratings veetodgnd +17v vsstodgnd 17v veetovss +22v digitaioutputs vee,dgnd digital inputs dmc (pin 13), clk (pin 12) . . . . . . . . . . . . . . vss, vee all other logic inputs. . . . . . . . . . . . . . . dgnd, +17v analog inputs/outputs agnd to dgnd (positive limitation) . . . . vee or vlrout* agnd to dgnd (negative limitation).vss or virout -20vt ain (pin 2), vrefi (pin 1), bufin(pin4) vee,vss irjct (pin 6), irout (pin 5). . . . . . . . +27v, agnd operating temperature range ad7555kn (plastic) . . . . . . . . . . . . . . . . . . 0 to +70c ad7555bd (ceramic) . . . . . . . . . . . . . . -25c to +85c storage temperature. . . . . . . . . . . . . . . . -65c to +1500c lead temperature (soldering, 10s). . . . . . . . . . . . . +300c power dissipation (package) plastic (ad7555kn) to+50c 1200mw derate above +50c by. . . . . . . . . . . . . . . . 12mw/c ceramic (ad7555bd) to+50c 1000mw derate above +50c by. . . . . . . . . . . . . . . . 10mw/c *whichever is the least positive. twhichever is the least negative. note: do not apply voltages to any ad7555 digital output, ain or vrefi before vee and vss are applied. additionally, the voltages at ain, vrefi or any digital output must never exceed vee and vss (if an op amp output is used to drive ain it must be powered by the ad7555 vee and vss supply voltages). do not allow any digital input to swing below dgnd. caution: esd (electro - static - discharge) sensitive device. the digital control inputs are zener protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. unused devices must be stored in conductive foam or shunts. the foam should be discharged to the destination socket before devices' are removed. system electrical characteristics (ta = 0 to +45 c) characteristics refer to the system of figures 6a and 6b. vee = +5v, vss = -5v, vrefi = +4.096v, error count n calibrated to zero at ta = +25c as per procedure on page 9 unless other- wise noted. switch leakages and limitations in temperature performance of auxiliary components (such as the integrating capacitor) cause performance degradations above +45 c conditions/comments :t20,000 counts :t200,000 counts (see note 1) 41/2 digit bcd 5 1/2 digit bcd (see notes 1 and 2) 4 1/2 digit bcd 5 1/2 digit bcd (see note 1) 4 1/2 digit bcd 5 1/2 digit bcd (see note 1) characteristic limit 4 1/2 digit bcd 5 1/2 digit bcd resolu tion relative accuracy :tl count max :tl0 count max count uncertainty due to noise (flicker) :tl/2 count max :t2 counts max conversion time 610ms max 1,760ms max notes: '41/2 digit mode; felk = 614.4khz, hren = low, rl = 360kn el = o.22;lf 5 1/2 digit mode; felk = 1.024mhz, hren = high, rl = 750kn el = o.22;lf 2 assumes voltage reference (vrefl) te of oppmfe. -3- obsolete
applying the ad7555 ad7555 pin description analog functions vrefl (pin 1): +4.096v reference inpur ain (pin 2): analog input voltage (:t2v full scale) agnd (pin 3): analog signal common ground bufin (pin 4): to external buffer amplifier input irout (pin 5): from integrator amplifier output irjct (pin 6): to integrator amplifier summing junction (logle input~s . i~"""""""';" oo..oo-. . comp' (pin 7): hren (pin 8): hold (pin 9): dmc (pin 13): clk (pin 12): sci (pin 15): supply inputs vcc (pin 28): vss (pin 14): dgnd (pin 21): .. .. input from the external comparator. high resolution enable, determines converter resolution hren = logic low, full scale = :t1.9999v (1001lv resolution) hren = logic high, full scale = :t1.99999v (lilv resolution) hold input hold = logic high, the adc converts and updates the displays continuously as per the timing diagram of figure 3. hold = logic low, the adc is reset and conversion is disabled. data; from the last complete conversion con1 tinues to be displayed. to ensure most! recent data is displayed, hold should! not be taken low when davis ! high. when hold returns high, . the next leading edge of dmc initiates a new conversion. display multiplexer clock, can be driven from an external logic source,' or with the addition of an external capacitor, will self oscillate. with an external capacitor of 10,ooopf, dmc oscillates at approximately 1.5khz at ~ 5% to 10% duty cycle, suitable for display purposes. clock input for maximum line rejec~ tion in the 41/2 digit mode; 50hz: fclk = 512khz (= 4.096mhz ';-8) 60hz: fclk = 614.4khz (= 4.915mhz ';-8) so/60hz: fclk = 409.6khz (= 3 .2768mhz.;- 8) for maximum line rejection in the 5 1/2 digit mode; so/60hz, fclk = 1.024mhz (=4.096mhz.;-4) serial count in. input to totalizing counter in the a07555. sci is normally connected to sco for direct count totalization. positive supply input (+5v) negative supply input (-5v) digital ground logic outputs b8 - b 1 (pins 17 - 20) (pin 22): d5 sco (pin 16): dav i(pin 10): data 0 4 6 8 9 overflow { +1 di~it -1 only + -4- bcd8 - bcd1 output, active high (sce table 1) 10-5 digit output, active low in 5 1/2 digit mode, stays high in 4 1/2 digit mode 10-4 - 10-1 digit outputs, active low 10 /overflow/polarity output, active low system conversion complete, goes high when conversion is complete, returns low on comparator crossing at end of phase 0 integration period. serial count out, a serial output pulse train proportional in length to the magnitude of ain. sco can b~ externally pulled high while da v = high to display the error count "n" for calibration purposes (see page 9). 8 data valid - when low, da v indicates that the data being presented on the bcd output bus is valid. da v goes high on the first positive edge of dmc after a conversion is complete and returns low two dmc pulses later. when it returns low, the digit counter is reset to do. this is termed the master reset. 8 b8 b4 b2 b1 led display when using 7447 segment decoder ,-, '...i . c (..1 , =, i 0 1 i t: '-. =.. ,_, " " . -, . . tab/e 1. output coding 8 ---- .- 04 - d 1 (pins 23- 27) .- do (pin 27): scc (pin 11): 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 obsolete
8 component limitations such as switch leakage, as well as operational amplifier offset voltage and bias current (and the temperature dependency of these errors), are major obstacles when designing high resolution integrating aid converters. the ad7555 however, utilizes a patented quad slope conver- sion technique (analog devices patent no. 3872466) to reduce the effects of such errors to second order effects. figure 1 shows a simplified quad slope integrator circuit. the various inputs agnd (analog ground), vrefb and ain (analog input) are applied in sequence to the integrator via switches 1-3 (see table 2), creating four slopes at the inte- grator output (phase 1-4 of figure 2). if the equivalent sum- ming junction voltage vs is precisely o.5vrefl, the phase 1 and phase 2 integration times are equal, indicating there are no input errors. if vs =1= 0.5vrefl (due to amplifier offset voltage, bias current, etc.), an error count "n" is obtained. the analog input integration cycle (phase 3) is subsequently lengthened or shortened by "n" counts, depending on whether the error was positive or negative. swo vref2 vs 0 vre'2 + vos + ibias r, + ilkgswo r, 48 figure 1. simplified quad slope integrator circuit phase 4 phase 0 phase 1 phase 2 phase 3 lain = +fsi -1-1 . ~ ~ i phase 4 -lain 0 01-1 phdse 4 lain 0 -fsi- ,ji",l "i i i ~-?-/ "" '-.. i ,'i' '-.. \' ," / ,i'"' 1 '-.. i j>.~ "'--"'-:---" 1 "" j '-.. i """ " "- ,- i klt i 1 m 4k, t . , 4k,t -too = '01 =__t02=-l=t03=12kl-nlt- l -to4= nt~ nt~ r,c, k" ik,+nlt 12k,+n-nlt l-t04=12k, +n+nlt notes' ,. for 4 1/2 digit mode, k, = 10.240 t = 4 x 1!iclk, where fclk is clock freouency at pin 12 2. for 5 1/2 digit mode, k, = 102.400 t = 2/iclk, where iclk is clock frequency at pin 12 3. n = error count due to amplifier offsets etc. and can be positive or negative. figure 2. quad slope integrator output 8 the final effect is to reduce the analog input error terms to second order effects. this can be proven by solving the dif- ferential equations obtained during the phase 1 through phase 4 integration periods. barring third (and higher) order effects, the solutions are given in equations 1 and 2. [ a1n ] . [ a1n ] [ 2 agnd ] n(ain;;'o)~kt vrefi +kt vref1- i - a + vrefi (1 + 2a) ' v---' . .r-- ' ideal term error 1 frm eqnl n . - k [ a1n ] k [ ain 1 ][ --a2 agnd (1 2 ) ] (ain <0)-- t vrefi - t vrefi - + vrefi + a ' ' . ideal term error term eqn2 where: n = number of counts appearing at ad75 5 5 serial count out pin corresponding to the analog input voltage, ain. ain = analog input voltage to be digitized kt = 40960 counts (4 1/2 digit mode) 409600 counts (5 1/2 digit mode) agnd = voltage at ad7555 pin 3 (agnd) measured with respect to vrefl and ain signal com- mon ground. (ideally, agnd = ov) . 2vs - vrefl a is an error term equal to v refl ideally a = 0 when vs = 0.5vrefl' note: vs = vref2 + yost + vos2 + ib2rl + isworl where: vref2 = 0.5vrefl if no error is present vosl = offset voltage of buffer amplifier al (required to buffer the effect of .0,ron of sw1 - sw2) vos2 = offset voltage of integrator amplifier a2 ib2rl = equivalent integrator amplifier offset voltage due to bias current of a2 iswori = equivalent integrator amplifier offset voltage due to swo leakage current. if agnd = 0, then the error terms of eqn 1 and 2 contain only second order effects due to a =1= o. thus, the ad7555 is a powerful tool which allows high precision system perform- ance to be obtained when using only moderate precision op amps. other advantages of the quad slope technique include bipolar operation using a single positive voltage reference, and the fact that since the comparator propagation delay is constant hysteresis effects are eliminated. (this is because the com- parator always approaches the zero crossing from the same direction). table 2. integrator equivalent input voltages and integration times -5- - switch equivalent closed input phase (figure 1) voltage integration time 0 sw3 vrefi - vs too=rici 1 sw2 agnd - vs toi = kit 2 sw3 vrefi - vs t02 = (kl + n)! 3 sw1 ain - vs t03 = (2k 1 - n)! 4 sw3 vrefi - vs t04 = (2kl + n:!:n)! 5 swo reset integrator obsolete
timing and control figure 3 shows the ad7555 timing. scc goes high at the end of sco indicating conversion is complete. da v goes high on the 1st leading edge of dmc after conversion is complete. new data is strobed into the data latches (see func- tional diagram) on the leading edge of the 2nd dmc. da v returns low on the leading edge of the 3rd dmc. bcd data is placed on b1, b2, b4, b8 on the positive edge of dmc while the digit counter is incremented on the negative edges of dmc. a reset phase (phase 0) is initiated on the 4th dmc after con- version is complete. scc returns low at the phase 0 comparator crossing indicating a conversion start. if the dmc oscillator is set up to free run (c8 in figure 6b causes dmc to run at about 1.5khz), the ad7555 will con- tinuously convert and update the displays. externally controlling the generation of dmc pulses provides a means of controlling data outputting for computer interface applications. pages 10 and 11 illustrate how to use this feature to interface the ad75 5 5 to a microprocessor. displa y the output data format of the ad7555 is multiplexed bcd as per the timing diagram of figure 3. the output code for- mat is shown in table 1. overflow causes digit 1 through digit 4 (digit 1 through digit 5 in 5 1/2 digit mode) to output a bcd 12 (1100). overflow does not affect digit o. therefore, a positive overflow is dis- played as ft. '-'1..' l'!..j and a negative overflow .as - /. u li ,_, '-, when using the 7447 seven-segment decoder.- printed circuit layout to ensure performance with the system specifications figures 5a and 5b show the recommended p.c. board layout for the ad7555. figure 4 shows the component overlay for figure 5a. oav ht ome after see update data latches to new data (2nd omc after see) phase 0 starts on phase 0 4th omc after sec comparator crossing (scc ireturns low) phase 0 t ~"as' negative- positive ain ain seo --.nnml lji j see omc oav i ' . i data not valid i; do=-=-=======~~ m~~~ =~ ~' ~ ~ 1 02 u _u- ---i ~ -------.--- ~ oj =~~~=~-=--=-] ~i 04= =-= =] lj5 -~ i gcd~a~;;08 =itb ,~ -- r , i-oat ~ a not valid 00 ~ -dlodata + 02 ~ new oata- ~ figure 3. timing diagram (self start dpm mode) al ternative size crystal c6 c4 r5 [u r ~ '4 f--w~r~~:r~~1 (29 3 3 ~ 3p ~ f g g{ ~(jj) 200 ~ ~ i ./ i ad30' a2 a'..- ,'1 i r'5 i x, : 01 10k [!] : i 4.7v-#- c3 r1750k , , :ro""':i i'f1rr1 r- -~ r4 r6 ~ l- i r~ 10k 10k r7 ih a a gl c1 ~ ~ ~~ ",,' oii"r ~ ~ 74c901 c8 0.01;~ ~ c:.> r9 r13 <51)0.01"f ]h ~r12n """""" ". ~ ~ ~ ~ ~71~9~~ i a~\ j ~ rl0: ~ ~ ~",~",w "",,'", ~r11 ~02~ l>'i<:~ ?c~? 04 ? 06 05 rl-14200 ds6 dllol ds5 dllol ds4 dll07 ds3 dl70l ds2 dllol 1 0 20 3 0 40 5 0 60 7 0 80 9 0 10 0 11 0 12 0 13 0 14 0 15 0 160 17 0 18 0 19 0 20 0 21 0 22 0 23 0 24 0 25 0 26 0 dav 27 0 vref1 28 0 cal 29 0 hren 30 0 hold 31 0 seo 32 0 88 33 0 81 34 0 84 35 0 82 36 0 dgnd 37 0 vee 8 pcb layout is reproduced on a one to one scale. note that a pad already exists on the pcb layout for an ad584lh voltage reference, suitable for 4 1/2 digit operation. 1 . - 3. 6 7 -. s. 9. 10. 11 . 12. 13 . 14. 15 . 16. 17 . 1s. 19 . 20 . 21 . 22. 23 . 24 . 25 . 26. if. 8 figure 5a. component side 18 figure 5b. foil side -7- obsolete
analog circuit set-up and operation the following steps, in conjunction with the analog circuitry of figure 6a explain the selection of the various component values required for proper operation. 1. selection of integrator components rl and cl improper selection of the integrator time constant (time constant = r 1 cl) may cause excessive noise due to the integrator output level being too low, or may cause non- linear operation if the integrator output attempts to exceed the rated output voltage of the amplifier. the integrator time constant rl cl must be: (vrefi )(ka) (fclk) (7v) ~rl cl~ (vrefl)(ka) (fclk)(vdd -5v) where: vdd is the integrator amplifier positive supply voltage fclk is the clock frequency at pin 12 ka = 8.2 x 104 (4 1/2 digit mode) or 4.0 x 10s (5 1/2 digit mode) the integrating capacitor must be a low leakage, low dielectric absorption type such as teflon (5 1/2 digit mode), polystyrene or polypropylene (41/2 digit mode). to mini- mize noise injection, the outside foil of cl must be con- agnd-ognd intertie { +2vtoo2vi ~ ain ain return 0---- voo. vss supply return r~ vref1 i note 3 l,vref1 return r420k note2 r5 200 r610k note 2 note 2 r15 10k nected to the output of the integrating amplifier, not to its summing junction. the recommended maximum value for rl in both the 4 1/2 digit and 5 1/2 digit mode is 750ksl. higher values may.cause noise injection. 2. determing conversion time maximum conversion time occurs when ain = -fs and is given by 8 4 1/2 digit mode tconvert = (325,760)(tclk) + rl cl 5 1/2 digit mode tconvert = (l,628,800)(tclk) + rl cl where: tclk = period of clk as measured at pin 12 rl cl = integrator time constant 3. initial calibration a. adjust vrefi so that the voltage at pin 1 (vrefl) of the ad7555 is +4.0960v. b. apply ov to ain and adjust r5 (vref2 adjust) for display 0.0000. (see optional calibration procedure on the next page for more precise calibration.) t voo = +15v rl 75ok note i i 2 cl0.24 8 logic and display circuitry the ad7555 possesses 41/2 digit accuracy with potential for 5 1/2 digit resolution. figure 6b shows the logic and display circuitry when operating the ad7555 with this high resolution. vcc' +5v i vcc = +5v +5v supply dgnd return note 4 8 ad7555 ic' vss notes. note 4 , for 4112 digit mode hren ipin 81 = logic low for 5 1/2 digit mode hren (pin 81 = logic high. 2. see clk pin description (page 4) for line rejection information. 3.06 and dso are not reouired for 4 1/2 digit operation. 4. calibration circuitry shown in figure 7. folk = '.o24mh, sec modifying the full scale display availability of the sco and sci terminals on the ad7555 provides flexibility for range-switching and modified data- format applications. for example, in the 5 1/2 digit mode, inserting a + 5 counter between sco and sci provides a full scale count at sci of 39,999 counts (199,999+5). vcc = +5v -5v 02 in914 to +15v figure 6b. logic and display circuitry (for 5 1/2 digit resolution) calibrating the ad7555 when the ad7555 is placed in the calibrate mode, any re- sulting error voltage in vs (summing junction voltage), due to drift, etc., will be contained in the resulting display. to display the error sc1 and seo must be taken high (only allowable when davis high). in the calibrate mode the display indicates +16.0480 ::!:n (+16.04800 ::!:n in 5 1/2 digit mode) where 16 indicates a blanked digit and n is a number represen ting the reference inpu t errors. this gives the change required in vref2 (::!:1:1vref2) for proper calibration (ie., n "" 0). the exact relationship between nand 1:1vref2 can be shown to be equal to: 8 (vrefl )n 1:1vref2 = 40,960 + n (vref1) ion (5 1/2 digit operation) 1:1 vref2 = 40,960 + ion (4 1/2 digit operation) for this capability to operate, ivref21 must be 1/2 vrefl ::!:2%. figure 7 shows the hardware connections for manual cali- bration. with the switch in the calibrate mode, adjust vref2 (potentiometer r5 as shown in figure 6a) until the display reads +16.0480 (+160.04800 in 5 1/2 digit mode). the ad7555 is now calibrated to the center of its error correcting range. return the switch to normal to resume normal conversion. +5v i 'norm i +5v ad7555 ain r3 cal sco sct ,3 dav dav dav ain ain : l- vrm i cal figure 7. hardware requirements for manual calibration of n = 0 -9- -- - r7 w'o '2 r8 '" 11 r9 ic2 10 rio 7447 9 r11 15 r12 14 r13 8 r7-r13 to 200" dgnd i 11 obsolete
microprocessor interfacing ad7555 as a polled input device (mcs-85 system) figure 8 shows an ad7555/8085 interface. the dmc clock inpu t of the ad75 5 5 is controlled by the microcompu ter via an output port of the 8155. typical timing for this interface mode is shown in figure 9. d-a v goes high on the 1st dmc leading edge after scc goes high. it returns low on the rising edge of the 3rd dmc pulse. digit zero is availabe on b1, b2, b4 and b8 at this time. the leading edge of the 4th dmc pulse initiates a new con- version and places digit 1 on b 1, b2, b4 and b8. table 3 shows a procedure for polling the ad7555. 8155 ad7555 system as per figure 6a and 6b dmc port c figure 8. ad7555 as a polled input device phase 4 comparator crossing phase 0 start irout pi;4se. polled dmc from 8155 j i l- scc 3l-j4l-j5l-j6l.j7 i i i i i --j ~ ~ i - i i i i i i i i previo~ dav bcd data to 8155 04 figure 9. timing diagram for operation as a polled input device (80851ad7555) put dmc iiigii . . --- i dav iiigii? !ll vs put dmc low put dmc low delay or putdmclligil main program put dmc low put dmc iiigii put dmc low read bcd data (digit 0) put d.\\c iiigil (initiates new conversion) put d,\\c low rcad bcd data (digit i) put dmc iiigil j put dmc low ",," 'to<' ,"""" rcad bcd data (digit 4) table 3. procedure for interfacing the ad7555 as a polled input device ad7555 as an interrupting input device (mcs-85 system) the ad7555 dmc oscillator provides dmc pulses until scc (system conversion complete) goes high. this causes an inter- rupt on the rst 7.5 line whereby the three-state buffer is activated and the microprocessor takes control of dmc. table 4 shows a procedure for using the ad7555 in this mode. fig- ure 10 shows the basic hookup. to 8085 rst7.5 8155 scc pdrtci~ i f:itfj'~g~bl 1/474126 \l three.state to dgnd buffer figure 10. ad7555 as an interrupting input device (mcs-85 system) interrupt entry (scc goes high causing interrupt) enable three-state buffer (74126 as shown in figure 10) put dmc high dav high' ~~~ put dmc low put dmc low put dmc high da v low' p/~o put dmc low read bcd data (digit 0) put dmc high put dmc low read bcd: data (digit 1) etc. read bcd data (digit 4) disable three-state buffer return to mam program table 4. procedure for interfacing the ad7555 as an inter- rupting input device -10- obsolete
0 opto-isolated serial interface figure 11 shows a serial interface to the mcs-85 system. this system can accommodate a remote interface where a common- mode voltage is expected to exist between system grounds. thc 8155 counterltimer is only 14 bits long, i.e., it can only count down from z14; therefore sca output from the ad7555 (zok counts full scale) has to be divided by 2 with consequent re- duction in system resolution. port c of the 8155 is configured as a control port. port b is an input port. this port configuration is necessary if sign infor- mation is required. magnitude information is obtained by isolated ad7555 power system ad7555 analog system per figure 6a -=-} +5v b2 ain analog input +5v return 8 +15v, -5v return note: system resolution can be increased by providing sufficient counter capacity to totalize 20k (or 200k) counts. interrogating the 8155 counter value. the rising edge of da v is used to cause an interrupt on the rst 7.5 line. the value (z14 - i~ i) in the 8155 counter should now be read. when dav returns low the 8155 counter is reset to ffh' sign information is checked at this time since do bcd data is present and stable on the bcd bus (see figure 9). the b2 line of the bcd bus is latched into port b by the signal on b stb i.e. the falling edge of da v. this causes a rising edge signal on bf (buffer full) to call the 8085 cpu to read the b2 bit. b2 bit is high for negative data, low for positive data. mcs-85 power system opto isolator port b timer! "';-2 counter ( section 10,000 counts full scale figure 11. optically isolated serial ad7555/mcs-85 interface (full scale = 10,000 counts) . -11- obsolete
outline dimensions dimensions shown in inches and (mm). 28-pin ceramic dip (suffix d) 8 =-tf -.~ 0.175 (4.45) 0.125 (3.18) 0.06 (3.05) 0.12 (1.53) ~ ~",~" 0.606 (15.4) i 0.008 (0.203) 0.58 (14.74) --j a ex) 1 m i ~ ,... it) u --h-- 0.02 (0.508) 0.015 (0.381) ~~ 0.105 (2.67) 0.095 (2.42) 0.065 (1.66) 0.045 (1.15) notes, lead no. 11s identified 8y dot or notch. leads are solder or tin plated kovar or alloy 42. 28-pin plastic dip (suffix n) 811 0.55 (13.97) -=r.47) ivvvvvvvvvvvvvvi 1.45 (36.83) .i. ~ ...! 1.44 (36.581 . o.,~ ~ ~ ~ ~ ~ ~ ~ ~ ~45) 0.065 11.661 0.02 (0.5081 0.105 (2.67) 0.12 (3.051 0.045 (1.15) 0.015 (0.3811 0.095 (2.42) notes, lead no.1 is identified by dot or notch. leads are gold.plated (50 microinches mini kovar or alloy 42. cavity lid is electricall y isolated. 8 0.16 (4.07) - rr 0.606 (15.4) ~ .14 (3.56) 0.594 (15.091 i \ 15. 0 ~ cj:! ::> z 0 w f- z a: a. 8 -12- obsolete
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